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DSP/Assignment_2_report/U1265119_Assignment2_report.tex
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@@ -11,6 +11,8 @@
\MakePerPage{footnote}
\usepackage{abstract}
\usepackage{graphicx}
% Create hyperlinks in bibliography
\usepackage{hyperref}
\usepackage[T1]{fontenc}
\usepackage[utf8]{inputenc}
@@ -70,7 +72,7 @@
\section{Background/Literature:\\Digital Signal Processor/Microcontroller
Overview}
A digital signal processor (DSP) is form of specialized microprocessor
A digital signal processor (DSP) is a form of specialized microprocessor
designed specifically for the processing of signals (such as audio signals
in this case).~\parencite[p.11-12]{libtak2006ieh}. The DSP is used as part
of a microcontroller that provides an interface for components such as
@@ -91,15 +93,14 @@
standard of DSPs available, it will be compared to three other digital signal
processors:
\begin{itemize}
\item Texas Instruments TMS320F2806x
\item Texas Instruments TMS320F2806
\item Freescale 56F8025
\item Analog Devices ADSP-2126x
\item Analog Devices ADSP-2126
\end{itemize}
\subsection{General Computing Factors}
Factors such as memory and CPU speed are factors that affect all computing
systems. These address the systems ability to perform calculations and
handle data.
Factors such as memory and CPU speed affect all computing systems. These
address the system's ability to perform calculations and handle data.
\subsubsection{Memory}
There are two types of memory that constitute the total memory of a
@@ -109,11 +110,33 @@
Most modern microcontrollers use flash memory for the storage of code
executed at runtime. This is known as ROM (read-only memory) and may be
reffered to as the ``program memory''. The size of this memory determines
the amount of code that can be stored at any one time in the processor.
This has implications with regaurds to the complexity of the program as
the amount of code that can be stored at any one time in the system.
This has implications with regards to the complexity of the program, as
insufficient program memory will limit the number of instructions that can
be used for programming.
\begin{table}[H]
\centering
\caption{DSP maximum available ROM memory}
\label{my-label}
\begin{tabular}{ll}
\textbf{Model} & \textbf{Program Memory}\\
dsPIC30F4013/PIC24 & 48kb \\
TMS320F2806 & 256kb \\
56F8025 & 32kb \\
ADSP-2126 & up to 4mb
\end{tabular}
\end{table}
These specifications indicate that the memory of the hardware used is
relatively small compared to other devices available. This limits the
complexity of programs that can be stored on the device. This accounts for
the limited complexity of designs described in section \ref{design}.
Clearly the ADSP has much more memory and has been designed for highly
complex applications, however the TMS32F2806 series would also have
sufficient memory for the programs designed in this task.
\paragraph{Data Memory}~\\
RAM (random-access memory) is volatile memory that is used for storing data
used when executing instructions. Unlike ROM memory, RAM can be both read
@@ -121,23 +144,62 @@
change as instructions are executed. This is used for the storage of data
such as audio buffer and parameter variables. The amount of RAM available
determines the maximum size of data such as buffers for audio delays. The
speed of the RAM is also integral to the overall performance of the system
speed of the RAM is also integral to the overall performance of the system,
as sufficient speed is required to read and write buffers as instructions
are executed by the CPU (see section \ref{CPU})
\begin{table}[H]
\centering
\caption{DSP maximum available RAM memory}
\label{my-label}
\begin{tabular}{ll}
\textbf{Model} & \textbf{RAM Size}\\
dsPIC30F4013/PIC24 & 2kb \\
TMS320F2806 & 100kb \\
56F8025 & 4kb \\
ADSP-2126 & up to 2mb
\end{tabular}
\end{table}
With the lowest memory of any processor in this comparisson, it is clear
that the dsPIC is lacking in this area. This creates severe limitations in
buffers and in the case of this project, resulted in severe delay line
limitations. Again, the TMS32F2806 series would have a far more acceptable
performance, allowing for multiple delays in a range of seconds as opposed
to the small fractions of a second possible with the dsPIC.
\subsubsection{System Bus}
The system bus handles data IO between components such as the CPU
and memory. For performance comparisson, the system bus's data width is
used to determine the maximum amount of memory that the CPU is able to
write directly to memory.
write to directly.
For example a 16BIT system can support a maximum of $2^{16}$ memory
addresses. This equals a maximum memory size of 64Kb of memory directly
accessible by the CPU. However, a 32BIT system can support $2^{32}$ memory
addresses which results in ~4GB of potential memory.
addresses which results in {\raise.17ex\hbox{$\scriptstyle\mathtt{\sim}$}}4GB of potential memory.
When analysing specifications of DSP systems it is important to seperate
the processing architechuture from the bit depth of the DSP components as
they affect different aspects of the system.
\begin{table}[H]
\centering
\caption{DSP bus architecture}
\label{my-label}
\begin{tabular}{ll}
\textbf{Model} & \textbf{Architecture Type}\\
dsPIC30F4013/PIC24 & 16BIT \\
TMS320F2806 & 32BIT \\
56F8025 & 16BIT \\
ADSP-2126 & 32/40BIT
\end{tabular}
\end{table}
The bus architecture is largely dictated by the total amount of memory
available to the system and this is reflected in the specification shown in
the table above. A 16BIT architecture is expected, given the 2kb of memory
supported by the dsPIC and is marginally faster than higher bit
architectures as there are less memory locations to allocate.
\subsubsection{CPU}\label{CPU}
The CPU (Central Processing Unit) is the component that executes
instructions and performs calculations on data. The speed at which the CPU
@@ -155,13 +217,37 @@
to an interupt before the processor has been able to complete them. This
can create in artefacts in output audio and create unexpected results.
It should be noted that this is not an entirely accurate measurement for
speed as different manufacturers have different definitions of a
``calculation''.~\parencite[p.3-4]{bdti2000cdp} For a more accurate
representation, an impartial benchmark from BDTI has been included where
possible.~\parencite[p.1]{bdti2013pg}
\begin{table}[H]
\centering
\caption{DSP CPU clock speed}
\label{my-label}
\begin{tabular}{lll}
\textbf{Model} & \textbf{CPU Clock Speed}
&\textbf{BDTI(sim)mark2000\textsuperscript{TM}}\\
dsPIC30F4013/PIC24 & 70MHz & 190\\
TMS320F2806 & 90MHz & n/a\\
56F8025 & 80MHz & 110\\
ADSP-2126 & 200MHz & 1090\\
\end{tabular}
\end{table}
From this it can be seen that the dsPIC and 56F8025 perform significantly
worse than the ADSP. This has a negative impact on samplerate as it must be
lowered to account for the lack of processing power. A sample rate of 8Khz
was used as opposed to the 44.1Khz samplerate that would be feasable on the
ADSP processor.
\paragraph{Architecture}~\\
The CPU architecture refers to the design of memory units and bus layouts.
The most common designs are von Neumann and Harvard architectures. The von
Neumann architecture combines program and memory data, allowing only serial
access of memory. By seperrating program and data memory, the Harvard
architecture allows for simulataneous access of data and program memory,
making it the more efficient of the two designs.
making it the more efficient of the two designs.~\parencite[p.320-321]{raf2014fdlm}
\begin{figure}[H]
\caption{von Neumann CPU architecture}
\makebox[\textwidth]{\includegraphics[width=0.75\textwidth]{neumann}}
@@ -170,11 +256,29 @@
\caption{Harvard CPU architecture}
\makebox[\textwidth]{\includegraphics[width=0.75\textwidth]{harvard}}
\end{figure}
\newpage
\begin{table}[H]
\centering
\caption{DSP bus architecture}
\label{my-label}
\begin{tabular}{ll}
\textbf{Model} & \textbf{Architecture Type}\\
dsPIC30F4013/PIC24 & Modified Harvard\\
TMS320F2806 & Harvard\\
56F8025 & Dual Harvard\\
ADSP-2126 & Super Harvard
\end{tabular}
\end{table}
Most modern DSPs use variations on the Harvard architecture for it's
performance. Variations of this have been used in all examples.
\section{DSP Specific Factors}
DSP specific factors relate to components specically affecting the systems
ability to handle audio signals. These will determine the quality of audio
manipulation and affect the computational requirements for the system.
manipulation and affect the computational requirements for the system. This
section briefly covers the computational impact of the DSP specific
factors.
\subsection{A/D \& D/A Converters}
A/D and D/A converters are required for audio input and output. Depending
@@ -185,12 +289,12 @@
converters that can perform as transparently as possible is essential for a
high quality system.
\subsection{Samplerate}
\subsubsection{Samplerate}
The samplerate defines the frequency at which a measurement will be taken
from the input audio. This is significant due to the quantity of
information returned from the A/D converter for processing. Higher sample
rates generates more measurements per second and thus requires more values
to be computed per second.
to be computed per second as discussed in section \ref{CPU}
\begin{figure}[H]
\caption{Illustration of sine wave sampling}
\makebox[\textwidth]{\includegraphics[width=\textwidth]{quantization}}
@@ -201,13 +305,13 @@
\makebox[\textwidth]{\includegraphics[width=\textwidth]{sampling_error}}
\end{figure}
\subsection{Bit Depth}
\subsubsection{Bit Depth}
The audio bit depth determines the accuracy to which amplitudes can be
differentiated. Higher bit depths result in a higher dynamic range in the
signal. This has implications for the converters as higher bit rates
require higher accuracy in generating values for each sample.
\section{Design/Analysis}
\section{Design/Analysis}\label{design}
Effect implementation wase largely dicatated by the limitations of the
dsPIC. As the device had sever memory and processing limitations, it was
not possible to create effects to the standard of the first assignment. As
@@ -219,11 +323,16 @@
to maximise available memory for the delay time. Through stripping out all
unnessesary features, a maximum delay size of 700 samples was acheived with
the addition of two UI switches that could be used for increasing and
decreasing delay size at runtime.
At a samplerate of 8Khz, this allowed for a single delay of \textgreater50ms defined
as the minimum for the definition of an echo
decreasing delay size at runtime. At a samplerate of 8Khz, this allowed
for a single delay of \textgreater50ms (93.750ms) defined as the minimum
for the definition of an echo
by Z{\"o}lzer~\citeyearpar[p.]{zolzer2011dafx}
\begin{figure}[H]
\caption{Echo example}
\makebox[\textwidth]{\includegraphics[width=0.4\textwidth]{echo_measure}}
\end{figure}
\subsection{Chorus}
To emulate the multiple instrument effect created by a chorus, three delays
of variable size were used. This created 3 phase shifted versions of the
@@ -234,7 +343,7 @@
\subsection{Reverb}
The reverb implementation involved a combination of an FIR and IIR filter
as defined by Z{\"o}lzer~\citeyearpar[p.]{zolzer2011dafx}. This performed
as defined by Z{\"o}lzer~\citeyearpar{zolzer2011dafx}. This performed
poorly when compared to the moorer reverb structure used in assignment 1,
however the complexity of such a structure would require superior
performance in almost all aspects of the system.
@@ -242,7 +351,7 @@
\subsection{User Interface}
The UI was designed using eight switches and the LCD to create a
navigatable menu that can be used for the section of effect, effect
navigatable menu that can be used for the selection of effect, effect
parameters and voculme control. The effect parameter menu is able to update
it's items dynamically based on the active effects. The desired effect can
then be selected by cycling through using repeated presses of the effects
@@ -257,22 +366,38 @@
demonstrate possibilities given a capable system.
\section{Results}
The results of real-time system implementation section should include:\\
Implementation on dsPIC based system\\
Testing and evaluation of the artificial reverberation system\\
Expected frequecy range based on samplerate
Overall, the results produced were not of a high standard. The low signal
to noise ratio, low sample rate and over-simplicity of designs made it
impossible to create results useable in a professional context. With a
sample rate of 8Khz, a cutoff sampling frequency of 4000khz was created.
this resulted in a telephony frequency response that removed higher
frequencies. poor converters added significant noise to the output which
further degraded results. However, steps were taken to create the best
quality outcome with the resources available.
\subsection{Echo}
Maxmum achieved.
Audio sound quality acheived
A maximum single tap delay of 750 samples was acheived through the
stripping of all unnessesary composnents. Without a user interface,
this was controlled through the use of two switches that
incremented/decremented the delay in values of 10 samples every 100ms.
The lack of a feedback loop resulted in a very simplistic delay with
equally simplistic results in terms of perception. A feedback was not
implemented to differentiate this from the reverb design.
\subsection{Chorus}
Maximum delay buffer size
Audio sound quality acheived
The implementation provided a perceptually similar alternative to the
unfeasable modulated delay line design from the previous assignment.
Each delay can be set to up to a maximum delay time of 250 samples.
This allows for manual shifting of phases to taste. Overall this
results in a functional alternative at the cost of perceptual quality.
\subsection{Reverb}
Audio sound quality acheived
The reverb
\section{Further Work}
The student should discuss the limitations of the system and how it could be developed further
Use of C as opposed to Flowcode
Faster system with more memory
Higher samplerate
\section{Conclusions}
The conclusion section should include:\\